1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor package and, more particularly, to a technique suitably applicable to the manufacturing of a resin-encapsulated semiconductor package formed by encapsulating a semiconductor chip with a resin.
2. Description of the Related Art
Demands on information and communication apparatuses are increasing yearly in the recent information age. Of these information and communication apparatuses, portable information apparatuses particularly increasingly demanded, such as a camcorder, a PHS (Personal Handyphone System), and a notebook personal computer, tend to be entirely made smaller and thinner to improve the portability. Accordingly, LSI packages incorporated into these apparatuses are naturally required to be made smaller and thinner.
Meanwhile, as the large scale integration of semiconductor elements advances, the chip area of a semiconductor gradually increases. Consequently, it becomes difficult to accommodate semiconductor elements in a package with required dimensions by a packaging method by which a chip is die-bonded to the die pad of a lead frame.
To eliminate this difficulty, a package structure as described in Japanese Patent Laid-Open No. 8-279575 has been proposed. FIG. 4 is a schematic sectional view showing this conventional package. In this package, conductive terminals are formed to vertically extend from electrodes on a semiconductor chip toward the surface of the semiconductor package and soldered to a pattern on a printed board.
In the semiconductor package shown in FIG. 4, a semiconductor chip 11 is encapsulated with an encapsulating resin 12. A plurality of chip electrodes 13 are formed on one surface (upper surface) of the semiconductor chip 11, and a thin flat die pad 22 is bonded to the other surface (lower surface) of the semiconductor chip 11 by a die-bonding material 18.
A protective film 21 having openings is formed on the surface, on which the chip electrodes 13 are formed, of the semiconductor chip 11, and in each of the openings at least part of the upper surface of the chip electrode 13 is exposed. Connecting holes 16 are formed in the encapsulating resin 12 in the direction of package thickness to communicate with the chip electrodes 13. The connecting holes 16 are filled with a conductive material, and this conductive material constitutes external connecting terminals 17.
A method of manufacturing the above semiconductor package will be described below with reference to FIGS. 5A to 5H.
First, as shown in FIG. 5A, chip electrodes 13 are formed on the upper surface of a semiconductor chip 11 on which circuits are formed.
Subsequently, as shown in FIG. 5B, a protective film 21 is formed on the surface, on which the chip electrodes 13 are formed, of the semiconductor chip 11 to prevent .alpha.-rays from entering the semiconductor chip 11 from the outside.
In FIG. 5C, a resist 25 is applied to the surface of the protective film 21 and patterned by normal photolithography.
In FIG. 5D, the protective film 21 over the chip electrodes 13 is removed by anisotropic etching to form openings in each of which at least part of the upper surface of the chip electrode 13 is exposed.
In FIG. 5E, a surface, on which the chip electrodes 13 are not formed, of the semiconductor chip 11 is fixed to one surface of a die pad 22 with a die-bonding material 18 serving as a buffer material interposed therebetween.
In FIG. 5F, the semiconductor chip 11 is located in the cavity of a mold 23, so that pins 24 projecting from the cavity surface of the mold 23 are run against the upper surfaces of the chip electrodes 13 exposed in the openings of the protective film 21.
In this state, a resin is injected to fill the cavity of the mold 23. Consequently, as shown in FIG. 5G, the semiconductor chip 11 is encapsulated with an encapsulating resin 12, and connecting holes 16 are formed in the encapsulating resin 12 to communicate with the chip electrodes 13 of the semiconductor chip 11.
Finally, as shown in FIG. 5H, the connecting holes 16 are filled with a conductive material to form external connecting terminals 17, thereby obtaining a semiconductor package.
In the conventional semiconductor package as described above, however, a mold must have portions for forming connecting holes. It is inevitable in the future to further miniaturize packages and increase the number of external connecting terminals such as encountered in logic products for specific applications. Therefore, when semiconductor packages are manufactured by the conventional technique, precise processing is required in the manufacture of a mold. This increases the cost of the mold.
Additionally, a mold is brought into contact with the surfaces of chip electrodes when connecting holes are formed, and this can damage the chip electrodes. To prevent the damage, it is necessary to form a buffer portion between a semiconductor chip and a die pad. Therefore, the number of manufacturing steps is increased.
Furthermore, the step of filling a package with external connecting terminals is necessary after molding and, if these terminals are formed as separate parts, the number of parts is increased. Therefore, the workability is lowered.